/*
    General purpose registers.
*/

module registerFile(
	input	wire 	    		clk, 
	input 	wire				gprWriteBackEn,      	// Enable register write back
	input	wire	[31:0] 	    gprWriteBackData,      	// Data for write back register
	input 	wire	[04:0] 	    gprWriteBackId,		   	// Register to write back
	input 	wire	[04:0] 	    gprId1, 				// Register number for out1
	input 	wire	[04:0] 	    gprId2, 				// Register number for out2
	output	wire	[31:0] 		gprOutput1,	      		// Data out 1, available one clock after outRegId1 is set
	output 	wire	[31:0] 		gprOutput2       		// Data out 2, available one clock after outRegId2 is set
);
	reg	[31:0]	gprs[31:0];
	
	always @(negedge clk)  begin
		if ( gprWriteBackEn && gprWriteBackId != 5'b0 ) begin
			gprs[gprWriteBackId] <= gprWriteBackData;
		end
	end	

    assign gprOutput1 = ( gprId1 == 5'b0 ) ? 32'b0 : gprs[gprId1];
    assign gprOutput2 = ( gprId2 == 5'b0 ) ? 32'b0 : gprs[gprId2];
endmodule